In some conventional multi-core microprocessors, the manufacturer may blow fuses on each core of the microprocessor to specify to each core the configuration of the cores on the multi-core microprocessor so that each core can statically determine from the fuse values which cores of the multi-core microprocessor are enabled to perform data processing in the system. Although this solution may have advantages, a disadvantage is that once the fuses are blown on the core for use in a first multi-core microprocessor configuration, the core with already-blown fuses may not be reconfigured in the event that demand for the second configuration arises. In some applications, such as performance testing or application of software that does not support multiple cores, it may be desirable to disable cores. Also, in many applications, not all of the cores of a microprocessor are needed, and even though cores may, under such circumstances, be put into a sleep state to conserve power, they still cause drag on the processor or system bus shared with the other cores. Drag can be caused, for example, by the core responding to snoop cycles. Also, individual cores of a multi-core microprocessor may be defective as manufactured or may fail during testing or operation. This may interfere with default coordination systems established, for purposes of inter-core communications, between the cores of the processor. Therefore, what is needed is a robust method for enabling reconfigurations of a multi-core microprocessor.